View AD1851R-J_7355504.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

functional block diagram 1 2 3 4 5 6 7 8 9 latch dac serial input register control logic ad1851/ ad1861 dgnd nc clk le data nc = no connect trim msb adj i out agnd sj r f v out 10 11 12 13 14 15 16 nc +v s ? s +v l i out rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a 16-bit/18-bit, 16 3 f s pcm audio dacs ad1851/ad1861 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features 110 db snr fast settling permits 16 3 oversampling 6 3 v output optional trim allows super-linear performance 6 5 v operation 16-pin plastic dip and soic packages pin-compatible with ad1856 & ad1860 audio dacs 2s complement, serial input applications high-end compact disc players digital audio amplifiers dat recorders and players synthesizers and keyboards product description the ad1851/ad1861 is a monolithic pcm audio dac. the ad1851 is a 16-bit device, while the ad1861 is an 18-bit de- vice. each device provides a voltage output amplifier, dac, serial-to-parallel register and voltage reference. the digital por- tion of the ad1851/ad1861 is fabricated with cmos logic elements that are provided by analog devices 2 m m abcmos process. the analog portion of the ad1851/ad1861 is fabri- cated with bipolar and mos devices as well as thin-film resistors. this combination of circuit elements, as well as careful design and layout techniques, results in high performance audio play- back. laser-trimming of the linearity error affords low total har- monic distortion. an optional linearity trim pin is provided to allow residual differential linearity error at midscale to be elimi- nated. this feature is particularly valuable for low distortion reproductions of low amplitude signals. output glitch is also small, contributing to the overall high level of performance. the output amplifier achieves fast settling and high slew rates, pro- viding a full 3 v signal at load currents up to 8 ma. when used in current output mode, the ad1851/ad1861 provides a 1 ma output signal. the output amplifier is short circuit protected and can withstand indefinite shorts to ground. the serial input interface consists of the clock, data and latch enable pins. the serial 2s complement data word is clocked into the dac, msb first, by the external clock. the latch enable signal transfers the input word from the internal serial input register to the parallel dac input register. the ad1851 input clock can support a 12.5 mhz data rate, while the ad1861 in- put clock can support a 13.5 mhz data rate. this serial input port is compatible with second generation digital filter chips used in consumer audio products. these filters operate at over- sampling rates of 2 3 , 4 3 , 8 3 and 16 3 sampling frequencies. the critical specifications of thd+n and signal-to-noise ratio are 100% tested for all devices. the ad1851/ad1861 operates with 5 v power supplies, mak- ing it suitable for home use markets. the digital supply, v l , can be separated from the analog supplies, v s and Cv s , for reduced digital crosstalk. separate analog and digital ground pins are also provided. power dissipation is 100 mw typical. the ad1851/ad1861 is available in either a 16-pin plastic dip or a 16-pin plastic soic package. both packages incorporate the industry standard pinout found on the ad1856 and ad1860 pcm audio dacs. as a result, the ad1851/ad1861 is a drop-in replacement for designs where 5 v supplies have been used with the ad1856/ad1860. operation is guaranteed over the temperature range of C25 c to +70 c and over the voltage supply range of 4.75 v to 5.25 v. product highlights l. ad1851 16-bit resolution provides 96 db dynamic range. ad1861 18-bit resolution provides 108 db dynamic range. 2. no external components are required. 3. operates with 5 v supplies. 4. space saving 16-pin soic and plastic dip packages. 5. 100 mw power dissipation. 6. high input clock data rates and 1.5 m s settling time permits 2 3 , 4 3 , 8 3 and 16 3 oversampling. 7. 3 v or 1 ma output capability. 8. thd + noise and snr are 100% tested. 9. pin-compatible with ad1856 & ad1860 pcm audio dacs.
rev. a C2C ad1851/ad1861Cspecifications (t a @ +25 8 c and 6 5 v supplies, unless otherwise noted) nc = no connect 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 16-bit latch 16-bit dac serial input register control logic ad1851 dgnd nc clk le data trim msb adj agnd sj nc ? s +v l +v s i out r f v out i out ad1851 functional block diagram nc = no connect 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 16-bit latch 16-bit dac serial input register control logic ad1851 dgnd nc clk le data trim msb adj agnd sj nc ? s +v l +v s i out r f v out i out ad1861 functional block diagram min typ max units digital inputs v ih 2.0 +v l v v il 0.8 v i ih , v ih = v l 1.0 m a i il , v il = 0.4 C10 m a accuracy gain error 1% midscale output voltage 10 mv drift (0 c to +70 c) total drift 25 ppm of fsr/ c bipolar zero drift 4 ppm of fsr/ c settling time (to 0.0015% of fsr) voltage output 6 v step 1.5 m s 1 lsb step 1.0 m s slew rate 9 v/ m s current output 1 ma step 10 w to 100 w load 350 ns 1 k w load 350 ns output voltage output configuration bipolar range 6 2.88 3.0 6 3.12 v output current 8ma output impedance 0.1 w short circuit duration indefinite to common current output configuration bipolar range ( 30%) 1.0 ma output impedance ( 30%) 1.7 k w power supply voltage +v l and +v s 4.75 5.25 v Cv s C5.25 C4.75 v temperature range specification 0 +25 +70 c operation C25 +70 c storage C60 +100 c warm-up time 1 min specifications subject to change without notice.
rev. a C3C ad1851 min typ max units resolution 16 bits total harmonic distortion + noise 0 db, 990.5 hz ad1851n-j, r-j 0.003 0.004 % ad1851n, r 0.004 0.008 % C20 db, 990.5 hz ad1851n-j, r-j 0.009 0.016 % ad1851n, r 0.009 0.040 % C60 db, 990.5 hz ad1851n-j, r-j 0.9 1.6 % ad1851n, r 0.9 4.0 % d-range* (with a-weight filter) C60 db, 990.5 hz ad1851n, r 88 db ad1851n-j, r-j 96 db signal-to-noise ratio 107 110 db maximum clock input frequency 12.5 mhz accuracy differential linearity error 0.001 % of fsr monotonicity 14 bits power supply current +i 10.0 13.0 ma Ci C10.0 C15.0 ma power dissipation 100 mw ad1861 min typ max units resolution 18 bits total harmonic distortion + noise 0 db, 990.5 hz ad1861n-j, r-j 0.003 0.004 % ad1861n, r 0.004 0.008 % C20 db, 990.5 hz ad1861n-j, r-j 0.009 0.016 % ad1861n, r 0.009 0.040 % C60 db, 990.5 hz ad1861n-j, r-j 0.9 1.6 % ad1861n, r 0.9 4.0 % d-range* (with a-weight filter) C60 db, 990.5 hz ad1861n, r 88 db ad1861n-j, r-j 96 db signal-to-noise ratio 107 110 db maximum clock input frequency 13.5 mhz accuracy differential linearity error 0.001 % of fsr monotonicity 15 bits power supply current +i 10.0 13.0 ma Ci C10.0 C15.0 ma power dissipation 100 mw *tested in accordance with eiaj test standard cp-307. specifications subject to change without notice. ad1851/ad1861
ad1851/ad1861 rev. a C4C absolute maximum ratings* v l to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v to 6.50 v v s to agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v to 6.50 v Cv s to agnd . . . . . . . . . . . . . . . . . . . . . . . . . C6.50 v to 0 v digital inputs to dgnd . . . . . . . . . . . . . . . . . . . C0.3 v to v l agnd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 v short circuit . . . . . . . . . . . . . . . . . indefinite short to ground soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300 c, 10 sec storage temperature . . . . . . . . . . . . . . . . . . C60 c to +100 c *stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. pin descriptions 1Cv s analog negative power supply 2 dgnd logic ground 3v l logic positive power supply 4 nc no connection 5 clk clock input 6 le latch enable input 7 data serial data input 8 nc no internal connection* 9v out voltage output 10 r f feedback resistor 11 sj summing junction 12 agnd analog ground 13 i out current output 14 msb adj msb adjustment terminal 15 trim msb trimming potentiometer terminal 16 v s analog positive power supply *pin 8 has no internal connection; -v l from ad1856 or ad1860 socket can be safely applied. ordering guide package model resolution thd + n option* ad1851n 16 bits 0.008% n-16 ad1851n-j 16 bits 0.004% n-16 ad1851r 16 bits 0.008% r-16 AD1851R-J 16 bits 0.004% r-16 ad1861n 18 bits 0.008% n-16 ad1861n-j 18 bits 0.004% n-16 ad1861r 18 bits 0.008% r-16 ad1861r-j 18 bits 0.004% r-16 *n = plastic dip package; r = small outline (soic) package. caution esd (electrostatic discharge) sensitive device. the digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy electro- static fields. unused devices must be stored in conductive foam or shunts. the protective foam should be discharged to the destination socket before devices are inserted. warning! esd sensitive device typical performance 175 150 125 100 75 50 25 2 4 6 8 10 12 14 clock frequency ?mhz pd ?mw power dissipation vs. clock frequency thd+n ?% 10 1 0.1 0.01 0.001 ?0 ?0 ?0 0 10 20 30 40 50 60 70 80 90 temperature ? c ?0db ?0db 0db thd vs. temperature
ad1851/ad1861 rev. a C5C total harmonic distortion total harmonic distortion plus noise (thd+n) is defined as the ratio of the square root of the sum of the squares of the val- ues of the first 19 harmonics and noise to the value of the funda- mental input frequency. it is usually expressed in percent (%). thd+n is a measure of the magnitude and distribution of lin- earity error, differential linearity error, quantization error and noise. the distribution of these errors may be different, depend- ing on the amplitude of the output signal. therefore, to be most useful, thd+n should be specified for both large (0 db) and small signal amplitudes (C20 db and C60 db). the thd+n figure of an audio dac represents the amount of undesirable signal produced during reconstruction and playback of an audio waveform. this specification, therefore, provides a direct method to classify and choose an audio dac for a desired level of performance. settling time settling time is the time required for the output of the dac to reach and remain within a specified error band about its final value, measured from the digital input transition. it is a primary measure of dynamic performance. midscale error midscale error, or bipolar zero error, is the deviation of the ac- tual analog output from the ideal output (0 v) when the 2s complement input code representing half scale is loaded in the input register. d-range distortion d-range distortion is equal to the value of the total harmonic distortion + noise (thd+n) plus 60 db when a signal level of C60 db below full scale is reproduced. d-range is tested with a 1 khz input sine wave. this is measured with a standard a- weight filter as specified by eiaj standard cp-307. signal-to-noise ratio the signal-to-noise ratio (snr) is defined as the ratio of the amplitude of the output when a full-scale output is present to the amplitude of the output with no signal present. this is mea- sured with a standard a-weight filter as specified by eiaj standard cp-307. reference i out dac r f audio output input latch data le clock serial-to-parallel conversion figure 1. ad1851/ad1861 functional block diagram functional description the ad1851/ad1861 is a complete monolithic pcm audio dac. no additional external components are required for op- eration. as shown in figure 1 above, each chip contains a volt- age reference, an output amplifier, a dac, an input latch and a parallel input register. the voltage reference consists of a bandgap circuit and buffer amplifier. this combination of elements produces a reference voltage that is unaffected by changes in temperature and age. the dac output voltage, which is derived from the reference voltage, is also unaffected by these environmental changes. the output amplifier uses both mos and bipolar devices to produce low offset, high slew rate and optimum settling time. when combined with the on-chip feedback resistor, the output op amp converts the output current of the ad1851/ad1861 to a voltage output. the dac uses a combination of segmented decoder and r-2r architecture to achieve consistent linearity and differential lin- earity. the resistors which form the ladder structure are fabri- cated with silicon chromium thin film. laser-trimming of these resistors further reduces linearity error, resulting in low output distortion. the input register and serial-to-parallel converter are fabricated with cmos logic gates. these gates allow the achievement of fast switching speeds and low power consumption. this contrib- utes to the overall low power dissipation of the ad1851/ ad1861.
ad1851/ad1861 rev. a C6C analog circuit considerations grounding recommendations the ad1851/ad1861 has two ground pins, designated analog and digital ground. the analog ground pin is the high quality ground reference point for the device. the analog ground pin should be connected to the analog common point in the system. the output load should also be connected to that same point. the digital ground pin returns ground current from the digital logic portions of the ad1851/ad1861 circuitry. this pin should be connected to the digital common point in the system. as illustrated in figure 2, the analog and digital grounds should be connected together at one point in the system. dgnd agnd 5v + ad1851/ad1861 5v analog ground digital ground 3 16 1 2 12 +5v +v l +v s ? s figure 2. recommended circuit schematic power supplies and decoupling the ad1851/ad1861 has three power supply input pins. the v s supplies provide the supply voltages to operate the linear portions of the dac including the voltage reference, output am- plifier and control amplifier. the v s supplies are designed to operate at 5 v. the +v l supply operates the digital portions of the chip includ- ing the input shift register and the input latching circuitry. the +v l supply is designed to operate at +5 v. decoupling capacitors should be used on all power supply pins. furthermore, good engineering practice suggests that these ca- pacitors be placed as close as possible to the package pins as well as to the common points. the logic supply, +v l , should be decoupled to digital common, while the analog supplies, v s , should be decoupled to analog common. the use of three separate power supplies will reduce feedthrough from the di gital portion of the system to the linear portion of the system, thus contributing to improved performance. however, three separate voltage supplies are not necessary for good circuit performance. for example, figure 3 illustrates a system where only a single positive and a single negative supply are available. in this example, the positive logic and positive analog supplies must both be connected to +5 v, while the negative analog sup- ply will be connected to C5 v. performance would benefit from a measure of isolation between the supplies introduced by using simple low pass filters in the individual power supply leads. +v l dgnd agnd ad1851/ad1861 analog ground digital ground 3 16 1 2 12 +v s ? s ?v +5v +5v figure 3. alternate recommended schematic as with most linear circuits, changes in the power supplies will affect the output of the dac. analog devices recommends that well regulated power supplies with less than 1% ripple be incor- porated into the design of any system using the ad1851/ad1861. optional msb adjustment use of an optional adjustment circuit allows residual differential linearity error around midscale to be eliminated. this error is especially important when low amplitude signals are being re- produced. in those cases, as the signal amplitude decreases, the ratio of the midscale differential linearity error to the signal am- plitude increases, thereby increasing thd. therefore, for best performance at low output levels, the op- tional msb adjust circuitry shown in figure 4 may be used to improve performance. the adjustment should be made with a small signal input (C20 db or C60 db). 15 14 1 trim 470k w 100k w 200k w msb adjust ? s figure 4. optional thd adjust circuit
ad1851/ad1861 rev. a C7C ad1851 digital circuit considerations ad1851 input data data is transmitted to the ad1851 in a bit stream composed of 16-bit words with a serial, msb first format. three signals must be present to achieve proper operation. they are the data, clock and latch enable (le) signals. input data bits are clocked into the input register on the rising edge of the clock signal. the lsb is clocked in on the 16th clock pulse. when all data bits are loaded, a low-going latch enable pulse updates the dac input. figure 5 illustrates the general signal require- ments for data transfer to the ad1851. data clock latch aaaaaaaaa s m b l s b figure 5. signal requirements for ad1851 figure 6 illustrates the specific timing requirements that must be met in order for the data transfer to be accomplished prop- erly. the input pins of the ad1851 are both ttl and 5 v cmos compatible. the input requirements illustrated in fig- ures 5 and 6 are compatible with data outputs provided by popular dsp filter chips used in digital audio playback systems. the ad1851 input clock can run at a 12.5 mhz rate. this clock rate will allow data transfer rates for 2 3 , 4 3 or 8 3 or 16 3 oversampling reconstructions. >40ns >40ns >30ns >30ns >15ns >40ns data clock latch >15ns >30ns >80.0ns >15ns figure 6. timing relationships of ad1851 input signals ad1861 digital circuit considerations ad1861 input data data is transmitted to the ad1861 in a bit stream composed of 18-bit words with a serial, msb first format. three signals must be present to achieve proper operation. they are the data, clock and latch enable (le) signals. input data bits are clocked into the input register on the rising edge of the clock signal. the lsb is clocked in on the 18th clock pulse. when all data bits are loaded, a low-going latch enable pulse updates the dac input. figure 7 illustrates the general signal require- ments for data transfer to the ad1861. data clock latch aaaaaaaaa l s b m b s figure 7. signal requirements for ad1861 figure 8 illustrates the specific timing requirements that must be met in order for the data transfer to be accomplished prop- erly. the input pins of the ad1861 are both ttl and 5 v cmos compatible. the input requirements illustrated in fig- ures 7 and 8 are compatible with data outputs provided by popular dsp filter chips used in digital audio playback systems. the ad1861 input clock can run at a 13.5 mhz rate. this clock rate will allow data transfer rates for 2 3 , 4 3 or 8 3 or 16 3 oversampling reconstructions. >40ns >40ns >30ns >30ns >15ns >40ns data clock latch >15ns >30ns >74.1ns >15ns figure 8. timing relationships of ad1861 input signals
ad1851/ad1861 rev. a C8C x1 st 16/18 dlo bco wco dro ym3434 clk +5v ad1851 clk latch data ad1851 clk latch data out out low pass filter low pass filter left output right output figure 9. ad1851 with yamaha ym3434 digital filter x1 st 16/18 dlo bco wco dro ym3434 clk +5v ad1861 clk latch data ad1861 clk latch data out out low pass filter low pass filter left output right output figure 10. ad1861 with yamaha ym3434 digital filter applications figures 9 through 12 show connection diagrams for the ad1851 and ad1861 and the yamaha ym3434 and the npc sm5813ap/apt digital filter chips.
ad1851/ad1861 rev. a C9C x1 dol bcko wcko dor sm5813ap/apt clk +5v ad1851 clk latch data out low pass filter left output right output cob ow20 +5v ow18 low pass filter out ad1851 clk latch data figure 11. ad1851 with npc sm5813ap/apt digital filter x1 dol bcko wcko dor sm5813ap/apt clk +5v low pass filter low pass filter left output right output ad1861 clk latch data out ad1861 clk latch data out cob ow20 ow18 figure 12. ad1861 with npc sm5813ap/apt digital filter
ad1851/ad1861 rev. a C10C other digital audio components available from analog devices 2 3 4 5 6 7 89 10 11 12 13 14 15 16 16-bit latch 16-bit dac serial input register control logic ad1856 ? s dgnd nc clk le data ? l +v l nc = no connect +v s trim msb adj i out agnd sj r f v out 1 i out ad1856 16-bit audio dac complete, no external components required 0.0025% thd low cost 16-pin dip or soic package standard pinout ? s clk le data adj i out agnd r f 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 voltage reference input and digital offset 20-bit dac ad1862 nc = no connect +v l ? l +v s trim ? s nr2 nr1 dgnd ad1862 20-bit audio dac 119 db signal-to-noise ratio 0.0016% thd+n 102 db d-range performance 1 db gain linearity 16-pin dip 2 3 4 5 6 7 89 10 11 12 13 14 15 16 18-bit latch 18-bit dac serial input register control logic ad1860 ? s dgnd nc clk le data ? l +v l nc = no connect +v s trim msb adj i out agnd sj r f v out 1 i out ad1860 18-bit audio dac complete, no external components required 0.0025% thd+n 108 db signal-to-noise ratio 16-pin dip or soic package standard pinout 1 2 3 4 5 6 7 8 9 10 11 12 trim msb i out agnd sj dr lr ck 18-bit latch reference 18-bit latch dgnd trim msb agnd sj dl ll 20 13 14 15 16 17 18 19 21 22 23 24 reference 18-bit d/a 18-bit d/a ad1864 + + v out ? s r f +v l +v s i out r f v out ? l ad1864 dual 18-bit audio dac complete, no external components 0.0025% thd+n 108 db signal-to-noise ratio cophased outputs 24-pin package
ad1851/ad1861 rev. a C11C outline dimensions dimensions shown in inches and (mm). n (plastic dip) package r (soic surface mount) package 1 8 9 16 0.299 (7.60) 0.050 (1.27) pin 1 0.419 (10.65) 0.012 (0.30) 0.104 (2.650) 0.013 (0.32) 0.042 (1.07) 0.030 (0.75) 0.413 (10.50) 0.019 (0.49)
c1458C7C10/90 printed in u.s.a. C12C

▲Up To Search▲

Price & Availability of AD1851R-J

	To Download AD1851R-J Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .